Ultrasonic thickness measurement and flaw detection devices that use ultrasonic transducers include a pulser circuit producing a high voltage excitation pulse delivered to the transducer, which in response produces an ultrasonic tuned frequency pulse designed to travel through the test piece under inspection. The ultrasonic pulse that travels into the test piece will produce ultrasonic reflections from flaws, voids or back-wall within the test piece called the return echos. Measuring the return echos allows a microprocessor based subsystem to calculate the thickness of the test piece or flaw depth within the test piece. Low frequency transducers are used for thicker test pieces and higher frequency transducers are used for thinner test pieces.
The generation of a high voltage excitation pulse is typically done with a high voltage power supply and a clocked counter to set the instance of time when the excitation pulse is generated and width of the excitation pulse. Based on the counter clock frequency and count value, this will allow the excitation pulse generation to be delayed at specific time intervals allowing it to be phase shifted as desired. By incrementally phase shifting the excitation pulse then digitally sampling each incremental phase shifted return echo, this will allow for a higher effective sampling rate of the return echo using a standard interleaving method. The time interval for phase shifting the excitation pulse has to be finer than the time interval for digitally sampling the return echo for interleaving to work in this manner.
There are other methods of interleaving and increasing the sampling rate that have inherent problems, such as using phase lock loops or delay components to fine delay the sample clock signal to the digital sampler. By incrementally delaying the clock to the digital sampler and re-sampling the return echo that appears at the same instance of time will create a higher effective sample rate but the use of phase lock loops can induce higher noise levels and clock jitter causing delay errors thus causing digital sampling rate errors. A delay component can also add higher noise and have significant delay variant from one circuit to the other.